1. Field
Example embodiments relate to a semiconductor memory device, and more particularly to a row active time control circuit and a semiconductor memory device having the row active time control circuit.
2. Description of the Related Art
Semiconductor memory devices may store received data in memory cells, and output the data stored in the memory cells to external devices. Semiconductor memory devices activate word-lines connected to memory cells in order to write data in the memory cells or read data from the memory cells. Conventionally, the word-lines are enabled based on and/or in response to an active command signal, and disabled based on and/or in response to a pre-charge command signal.
FIG. 1 is a timing diagram illustrating an operation of a conventional semiconductor memory device when a pre-charge command signal is generated after a maximum retention time of a row active control signal.
Referring to FIG. 1, a row active master signal PR_A is enabled (e.g., transitions from a low to high state) based on and/or in response to an active command signal ACT. The row active master signal PR_A is disabled (e.g., transitions from a high to low state) based on and/or in response to a pre-charge command signal PRE. A word-line enable signal WLE that activates word-lines is enabled or disabled based on and/or in response to the row active master signal PR_A.
Generally, a boosted voltage whose voltage level is higher than a power voltage level is applied to gates of memory cells when a word-line is activated. Typically, as the density of semiconductor memory devices increases, the size of transistors in the semiconductor memory devices gradually decreases. Further, transistors may be damaged when a high voltage such as the boosted voltage is applied to gates of the transistors for a long time. Damaged transistors are more likely to malfunction.
When a semiconductor memory device operates properly, the pre-charge command signal PRE is generated, and the word-line enable signal WLE is disabled within a maximum retention time tRAS_MAX of a row active control signal that the semiconductor memory device allows. FIG. 1 indicates the word-line enable signal is not disabled until after the maximum retention time tRAS_MAX. If the pre-charge command signal PRE is generated too late after the active command signal ACT is generated, memory transistors of a memory cell array may be stressed.